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freescale semiconductor product brief document num ber: mc56f8025pb rev. 0, 09/2006 contents ? freescale semiconductor, inc., 2006. all rights reserved. ? preliminary?subject to change without notice 1 56f8025 description the 56f8025 is a member of the 56800e core-based family of digital signal controllers (dscs). it combines, on a single chip, th e processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, a nd compact program code, the 56f8025 is well-suited for many applications. the 56f8025 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inve rters, smart sensors, fire and security systems, sw itched-mode power supply, power management, a nd medical monitoring applications. the 56800e core is based on a dual harvard-style architecture consisting of th ree execution units operating in parallel, allowing as many as six operations per instruction cycle. the mc u-style programming model and optimized instruction set allow straightforward generation of efficient, co mpact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. 1 56f8025 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 digital signal controller core . . . . . . . . . . . . . . . . . . . . . 3 3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 peripheral circuits for 56f8025. . . . . . . . . . . . . . . . . . . . 3 5 recommended operating conditions . . . . . . . . . . . . . . . 5 6 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 56f8025 package and pin-out . . . . . . . . . . . . . . . . . . . . 7 56f8025 digital signal controller product brief
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice 56f8025 description freescale semiconductor 2 the 56f8025 supports program execution from intern al memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 56f8025 also offers up to 35 general-purpose input/output (gpio) lines, depe nding on peripheral configuration. the 56f8025 digital signal contro ller includes 32kb of program flash and 4kb of unified data/program ram. program flash memory can be independently bulk erased or erased in pages. program flash page erase si ze is 512 bytes (256 words). a full set of programmable periphe rals ? pwm, adcs, qsci, qspi, i2 c, pit, quad timers, dacs, and analog comparators ? supports various applications. each peripheral can be independently shut down to save power. any pin in these peripherals can also be used as general pur pose input/outputs (gpios). figure 1. 56f8025 block diagram programmable interval timer program controller and hardware looping unit data alu 16 x 16 + 36 -> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller 4 unified data / program ram 2k x 16 pdb pdb xab1 xab2 xdb2 cdbr qspi or pwm or i 2 c or tmra or gpiob ipbus bridge (ipbb) system bus control r/w control memory pab pab cdbw cdbr cdbw jtag/eonce port or gpiod digital reg analog reg low-voltage supervisor v cap v dd v ss_io v dda v ssa 4 reset or gpioa ad0 4 clock generator* system integration module p o r o s c pwm or tmra or cmp or gpioa *includes on-chip relaxation oscillator cop/ watchdog ad1 4 program memory 16k x 16 flash adc or cmp or gpioc qsci or pwm or i 2 c or tmra or gpiob 3 3 i 2 c or cmp or gpiob 2 2 xtal, clkin, or gpiod extal or gpiod 2 11 dac
digital signal controller core 56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 3 2 digital signal controller core ? efficient 16-bit 56800e family digital signal controller (dsc) engine with dual harvard architecture ? as many as 32 million instructions per second (mips) at 32mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt st ack with depth li mited only by memory ? jtag/enhanced on-chip emulation (once) for unobtrusive, processor speed-independent real-time debugging 3memory ? dual harvard architecture permits as many as th ree simultaneous accesse s to program and data memory ? flash security and protection that prevent unauthor ized users from gaining access to the internal flash ? on-chip memory ? 32kb of program flash ? 4kb of unified data/program ram ? eeprom emulation capability using flash 4 peripheral circuits for 56f8025 ? one multi-function six-output puls e width modulator (pwm) module ? up to 96mhz pwm operating clock ? 15 bits of resolution ? center-aligned and edge-aligned pwm signal mode ? four programmable fault inputs wi th programmable digital filter ? double-buffered pwm registers ? each complementary pwm signal pair allows selection of a pwm supply source from: ? pwm generator ? external gpio ? internal timers ? analog comparator outputs ? adc conversion result which compares with values of adc high- a nd low-limit registers to set pwm output
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice peripheral circ uits for 56f8025 freescale semiconductor 4 ? two independent 12-bit analog- to-digital converters (adcs) ? 2 x 4 channel inputs ? supports both simultaneous and sequential conversions ? adc conversions can be synchr onized by both pwm and timer modules ? sampling rate up to 2.67msps ? 16-word result buffer registers ? two internal 12-bit digita l-to-analog converters (dacs) ? 2 microsecond settling time when output swing from rail to rail ? automatic waveform generation generates s quare, triangle and sawtooth waveforms with programmable period, upda te rate, and range ? one 16-bit multi-purpose quad timer module (tmr) ? up to 96mhz operating clock ? eight independent 16- bit counter/timers with cascading capability ? each timer has capture and compare capability ? up to 12 operating modes ? one queued serial communication interf ace (qsci) with lin slave functionality ? full-duplex or single-wire operation ? two receiver wake-up methods: ? idle line ? address mark ? four-bytes-deep fifos are availabl e on both transmitter and receiver ? one queued serial peripheral interfaces (qspi) ? full-duplex operation ? master and slave modes ? four-words-deep fifos available on both transmitter and receiver ? programmable length transactions (2 to 16 bits) ? one inter-integrated circuit (i 2 c) port ? operates up to 400kbps ? supports both master and slave operation ? supports both 10-bit address mode and broadcasting mode ? three 16-bit programmable interval timers (pits) ? two analog comparators (cmps) ? selectable input source in cludes external pins, dacs ? programmable output polarity ? output can drive timer input, pwm fault input, pwm source, external pin output and trigger adcs
recommended operating conditions 56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 5 ? output falling and rising edge detect ion able to generate interrupts ? computer operating properly (cop )/watchdog timer capable of sel ecting different clock sources ? up to 35 general-purpose i/o (g pio) pins with 5v tolerance ? integrated power-on reset (por) an d low-voltage interrupt (lvi) module ? phase lock loop (pll) provides a high-sp eed clock to the core and peripherals ? clock sources: ? on-chip relaxation oscillator ? external clock: crystal oscillator, ceram ic resonator, and external clock source ? jtag/eonce debug programming in terface for real-time debugging 5 recommended operating conditions table 1. recommended operating conditions (v refl x = 0v, v ssa = 0v, v ss = 0v) characteristic symbol notes min typ max unit supply voltage v dd, v dda 33.33.6 v adc reference voltage high v refhx 3.0 v dda v voltage difference v dd_io to v dda v dd -0.1 0 0.1 v voltage difference v ss_io to v ssa v ss -0.3 0 0.3 v device clock frequency using relaxation oscillator using external clock source fsysclk 1 0 32 32 mhz input voltage high (digital inputs) v ih pin groups 1, 2 2.0 5.5 v input voltage low (digital inputs) v il pin groups 1, 2 -0.3 0.8 v oscillator input voltage high xtal not driven by an external clock xtal driven by an external clock source v ihosc pin group 4 v dda - 0.8 2.0 v dda + 0.3 v dda + 0.3 v oscillator input voltage low v ilosc pin group 4 -0.3 0.8 v analog input voltage v ia pin group 3 0.0 v dda v
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice product documentation freescale semiconductor 6 6 product documentation the documents listed in table 2 are required for a complete description and proper design with the 56f8025. documentation is available from local freesca le distributors, frees cale semiconductor sales offices, freescale literature dist ribution centers, or online at: http://www.freescale.com output source current high at v oh min.) 1 when programmed for low drive strength when programmed for high drive strength i oh pin group 1 pin group 1 ? ? -4 -8 ma output source current low (at v ol max.) 1 when programmed for low drive strength when programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 ? ? 4 8 ma ambient operating temperature (automotive) t a -40 125 c ambient operating temperature (extended industrial) t a -40 105 c flash endurance (program erase cycles) n f t a = -40c to 125c 10,000 ? cycles flash data retention t r t j <= 70c average 15 ? years 1 total chip source or sink current cannot exceed 75ma table 2. 56f8025 chip documentation topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm 56f802x and 56f803x peripheral reference manual detailed description of peripherals of the 56f802x and 56f803x family of devices mc56f80xxrm 56f802x and 56f803x serial bootloader user guide detailed description of the serial bootloader in the 56f802x and 56f803x family of devices 56F80XXBLUG 56f8025 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8025 56f8025 errata details any chip issues that might be present mc56f8025e table 1. recommended operating conditions (continued) (v refl x = 0v, v ssa = 0v, v ss = 0v) characteristic symbol notes min typ max unit
56f8025 package and pin-out 56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 7 7 56f8025 package and pin-out figure 2. top view, 56f8025 48-pin lqfp package peripheral pins in bold identify the reset state in table 3 . orientation mark pin 12 pin 34 pin 23 pin 1 gpiob6 / rxd0 / sda / clkin gpiob1 / ss0 / sda gpiob7 / txd0 / scl gpiob5 / ta1 / fault3 / clkin gpioa9 / fault2 / ta3 / cinb1 gpioa11 / cinb2 gpioc4 / anb0 & cinb3 gpioc5 / anb1 gpioc6 / anb2 / v refhb gpioc7 / anb3 / v reflb v dda v ssa gpioc3 / ana3 / v refla gpioc2 / ana2 / v refha gpioc1 / ana1 gpioc0 / ana0 & cina3 v ss_io v cap tck / gpiod2 reset / gpioa7 gpiob3 / mosi0 / ta3 / psrc1 gpiob10 / couta_a gpioa3 / pwm3 gpioa2 / pwm2 gpioa4 / pwm4 / ta2 / fault1 gpiob0 / sclk0 / scl v dd_io v ss_io gpioa5 / pwm5 / ta3 / faulta2 gpioa8 / faulta1 / ta2 / cina1 gpioa10 / cina2 gpioa6 / fault0 / ta0 gpiob2 / miso0 / ta2 / psrc0 tdo / gpiod1 tms / gpiod3 gpiob11 / coutb_a tdi / gpiod0 gpioa0 / pwm0 gpioa1 / pwm1 gpiod4 / extal gpiod5 / xtal / clkin v ss_io v dd_io v cap
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice 56f8025 package and pin-out freescale semiconductor 8 table 3. 56f8025 44-pin lqfp package identification by pin number 1 1 alternate signals are in italic pin # signal name pin # signal name pin # signal name pin # signal name 1 gpiob6 rxd0 / sda / clkin 12 v ssa 23 gpiob2 miso0 / ta2 / psrc0 34 v cap 2 gpiob1 ss0 / sda 13 gpioc3 ana3 / v refla 24 gpioa6 fault0 / ta0 35 v dd_io 3 gpiob7 txd0 / scl 14 gpioc2 ana2 / v refha 25 gpioa10 cina2 36 v ss_io 4 gpiob5 ta1 / fault3 / clkin 15 gpioc1 ana1 26 gpioa8 fault1 / ta2 / cina1 37 gpiod5 xtal / clkin 5 gpioa9 fault2 / ta3 / cinb1 16 gpioc0 ana0 & cina3 27 gpioa5 pwm5 / ta3 / fault2 38 gpiod4 extal 6 gpioa11 cinb2 17 v ss_io 28 v ss_io 39 gpioa1 pwm1 7 gpioc4 anb0 &cinb3 18 v cap 29 v dd_io 40 gpioa0 pwm0 8 gpioc5 anb1 19 tci gpiod2 30 gpiob0 sclk0 / scl 41 tdi gpiod0 9 gpioc6 anb2 / v refhb 20 gpiob10 couta_a 31 gpioa4 pwm4 / ta2 / fault1 42 gpiob11 coutb_a 10 gpioc7 anb3 / v reflb 21 reset gpioa7 32 gpioa2 pwm2 43 tms gpiod3 11 v dda 22 gpiob3 mosi0 / ta3 / psrc1 33 gpioa3 pwm3 44 tdo gpiod1
56f8025 package and pin-out 56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 9 figure 3. 56f8025 44-pin lqfp mechanical information please see www.freescale.com for the most current case outline.
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 10 this page is intentionally blank
56f8025 digital signal controller product brief, rev. 0 preliminary?subject to change without notice freescale semiconductor 11 this page is intentionally blank
document number: mc56f8025pb rev. 0 09/2006 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . preliminary?subject to change without notice

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